Reconfigurable elements are designed differently depending on the application to be executed and are designed to be consistent with the application. A reconfigurable architecture is understood in the present case to refer to modules or units (VPUs) having a configurable function and/or interconnection, in particular integrated modules having a plurality of arithmetic and/or logic and/or analog and/or memory and/or internally/externally interconnected modules arranged in one or more dimensions and interconnected directly or via a bus system.
The generic type represented by these modules includes in particular systolic arrays, neural networks, multiprocessor systems, processors having multiple arithmetic units and/or logic cells and/or communicative/peripheral cells (IO), interconnection and network modules, e.g., crossbar switches as well as known modules of the FPGA, DPGA, Chameleon, VPUTER, etc. types. Reference is made in particular in this connection to the following patents and applications by the present applicant: DE 44 16 881 A1, DE 197 81 412 A1, DE 197 81 483 A1, DE 196 54 846 A1, DE 196 54 593 A1, DE 197 04 044.6 A1, DE 198 80 129 A1, DE 198 61 088 A1, DE 199 80 312 A1, PCT/DE 00/01869, DE 100 36 627 A1, DE 100 28 397 A1, DE 101 10 530 A1, DE 101 11 014 A1, PCT/EP 00/10516, EP 01 102 674 A1, DE 198 80 128 A1, DE 101 39 170 A1, DE 198 09 640 A1, DE 199 26 538.0 A1, DE 100 50 442 A1, as well as PCT/EP 02/02398, DE 102 40 000, DE 102 02 044, DE 102 02 175, DE 101 29 237, DE 101 42 904, DE 101 35 210, EP 01 129 923, PCT/EP 02/10084, DE 102 12 622, DE 102 36 271, DE 102 12 621, EP 02 009 868, DE 102 36 272, DE 102 41 812, DE 102 36 269, DE 102 43 322, EP 02 022 692, PACT40. Reference is made to the documents below by using the applicant's internal reference notation. These are herewith incorporated to the full extent for disclosure purposes.
The aforementioned architecture is used as an example for illustration and is referred to below as a VPU. This architecture is composed of any arithmetic or logic cells (including memories) and/or memory cells and/or interconnection cells and/or communicative/peripheral (IO) cells (PAEs) which may be arranged to form a one-dimensional or multidimensional matrix (PA), which may have different cells of any design. Bus systems are also understood to be cells here. The matrix as a whole or parts thereof are assigned a configuration unit (CT, load logic) which configures the interconnection and function of the PA. The CT may be designed as a dedicated unit according to PACT05, PACT10, PACT17, for example, or as a host microprocessor according to P 44 16 881.0-53, DE 101 06 856.9; it may be assigned to the PA and/or implemented with or through such a unit.